A circuit has four inputs A, B, C and D. These inputs are applied to a circuit that converts the inputs into an excess-3 code format and then further displays them on the 7-segment indicator. Thus, for input side, we will have 3 to 12 as our original 0 to 9 BCD values because the inputs are excess-3 codes. The rest of the input combinations will generate an output of don’t cares. However, the output on the 7-segement indicator should represent the correct BCD value. Design a circuit for the above-mentioned process. Your design should only include NAND gates and INVERTERS.

Hint: If the excess-3 code input applied is 7, it should represent the BCD value 4 as output on the 7-segment indicator. "For the design and implementation problems, you may be able to follow the procedure as shown below (not all steps may be required):
I. Derive the truth table for the assigned problem
II. Use K-Maps to derive logic equations in SOP or POS form depending on whether NAND or NOR gates are required.
III. Draw the circuit of AND and OR gates, trying to minimise the number of gates required by using common gates where appropriate. Factoring/Multiplying out is required in some cases.
IV. Convert to NAND or NOR gates if specified in the problem.
V. Think of how your logic will be utilised in the VHDL program and decide your entity, architecture, test-bench etc.
VI. Identify the possible timing simulation scenarios and use the testbench to evaluate your logic.
VII. Where applicable, demonstrate how the logic will operate on the Nexys board, using the peripherals available on the Nexys board (Slide Switches, LEDS, 7- segment displays, built-in clock, etc.)."