The Verilog code is /* 4 to 2 priority encoder */
Data flow description is given below:
module two_four_decoder (
input wire [1:0] w, input wire En, output wire [3:0] y);\\input output declaration
assign y[0]= (En & (~w[1] & ~w[0]));\\y0=1 when w1 and w0 are 00;
assign y[1]= (En & (~w[1] & w[0]));\\y1=1 when w1 and w0 are 01
assign y[2]= (En & (w[1] & ~w[0]));\\y2=1 when w1 and w0 are 10
assign y[3]= (En & (w[1] & w[0]));\\y3=1 when w1 and w0 are 11
endmodule
/* 4 to 2 encoder*/
module four_two_encoder(input wire [3:0] w, output wire [1:0] y, output wire zero);
assign y[1]=w[3] | w[2];
assign y[0]=w[3] | w[1];
assign zero= w[3] | w[2] | w[1] | w[0];
endmodule
/* 4 to 2 priority encoder */
module priority_encoder(input wire [3:0] w, output wire [1:0] y, output wire zero);
assign y[1]=w[3] | w[2];
assign y[0]=w[3] | (~w[2] & w[1]);
assign zero= w[3] | w[2] | w[1] | w[0];
endmodule
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