Assume a 64 bit processor with instruction set similar to mips in that the only memory instructions are a brief description of what it does load and store to/from register, and all other instructions are r-forma a brief description of what it doest (suitably extended for 64 bits). you have 64 registers and a 5 stage pipeline. l1 cache returns in 1 cycle, l2 cache takes 4 cycles for an l1 miss. cache is write-through handled in hardware without cpu action, memory has a 20 cycle initial delay and after that supplies one word per cycle, and an l2 miss has a 40 cycle cost and loads 20 words into cache. you are asked to design a 12 core chip where each core is as described, and will run at 2ghz. what memory bandwidth is required to support all 12 cores