Write a Verilog module called simplified to implement the simplified circuit obtained from the K-Map simplification process in Step 6. Write a test bench to apply the same inputs to both the original module and simplified module. Name the output for the original function origin, and name the output for the simplified function simple. In your test bench, make sure all the possible value combinations that the inputs can have for the original and simplified functions are included. In this case, we have 4 inputs and will have 24 = 16 input combinations.