Consider the following delays for computation in each of the pipeline stages in a MIPS processor: IF:150psID:250psEX: 200 ps MEM:250psWB: 100 ps Given this, what is the latency of a load instruction in a five stage pipelined implementation of this MIPS processor?1000ps1250ps85025010 points Caches exploit and locality to reduce the overall time spent by processors in accessing data from the memory. 10 points Which of the following performance metrics does pipelining improve? Instruction execution time Instruction throughput Both of the above options None of the above